The invention relates to a method of manufacturing a semiconductor device and a semiconductor wafer, and can be utilized suitably for manufacturing a semiconductor device using a technique for thinning a semiconductor wafer by grinding only an inner portion of the semiconductor wafer except for its outer periphery when grinding a rear surface of the semiconductor wafer (hereinafter, referred to as TAIKO process), in particular.
Japanese Unexamined Patent Application Publication No. 2007-036129 discloses a technique in which with a passivation film left in a region some millimeters from the outer periphery of a wafer, the passivation film on a scribe line is removed, thereafter a rear surface of the wafer is ground, and the wafer is cut along the scribe line, to cut out the individual chips.
Further, Japanese Unexamined Patent Application Publication No. 2015-147231 discloses a wafer the top surface of which is provided with a device region including a plurality of devices and an outer peripheral excessive region for surrounding the device region and the rear surface of which is provided with a ring reinforcing portion at a position corresponding to the outer peripheral excessive region.
Further, Japanese Unexamined Patent Application Publication No. 2015-177170 discloses a technique in which with a protective tape adhered to the top surface of a wafer, a dividing groove is formed in the boundary of a ring shaped convex portion and concave portion, a dicing tape is adhered to the rear surface of the wafer, the protective tape and the ring shaped convex portion are removed from the top surface, hence to divide the device forming region of the wafer into the individual devices.
The TAIKO process is effective in reducing warpage of a semiconductor wafer and avoiding intensity reduction of the wafer even when thinning the wafer to about 60 μm to 120 μm. However, when cutting the outer peripheral portion of the semiconductor wafer in a ring shape, triangular chipping occurs in the outer periphery of the remaining semiconductor wafer and this triangular chipping disadvantageously triggers crack in the remaining semiconductor wafer.
Other problems and novel characteristics will be apparent from the description of the specification and the attached drawings.